1. Field of the Invention
The present invention relates to an electrostatic discharge protection device for protecting externally generated semiconductor integrated circuit from a static electricity.
2. Description of the Related Arts
Static electricity is often externally generated, for example, from a human body or an assembling/transfer robot through a lead and the like, during the assembly of the semiconductor integrated circuit or the transfer of a packaged chip. If a large amount of charge due to static electricity is transferred to the chip, the gate oxide film of dielectric gate transistors formed within the chip can be ruptured by a high voltage, or the polysilicon and silicon substrates in gate electrodes can become fused to each other by heating. This results in degraded semiconductor integrated circuit performance. Therefore, semiconductor integrated circuits include devices which can protect against static electricity up to thousands of volts. The component performing such a function is referred to as an electrostatic discharge(ESD) protection device. A well known electrostatic protection device is disclosed in the U.S. Pat. No. 3,407,339 and is shown in FIG. 1.
Referring to FIG. 1, a conventional electrostatic discharge protection device uses a P-channel dielectric gate MOS transistor (hereinafter referred to as a "PMOS transistor") in which a gate 1 and a P+type source (or drain) 2 are coupled to an input voltage Vx, and a P+ type drain (or source) 3 to a substrate voltage Vss. As can be seen from FIG. 1(B), a PNP type parasitic bipolar transistor composed of P+ type diffused regions 2 and 3 and a bulk 4 (n type substrate or n type well) is also formed. The potential of the substrate voltage Vss is placed between a negative voltage and 0 volt, and the bulk 4 is coupled to the substrate voltage Vss or to the back gate voltage of another potential. That is, the conventional electrostatic discharge protection device as shown in FIG. 1 is featured in that the gate and source, or the gate and drain, are maintained at an equipotential. Thus, the protection device against the static electricity between the input voltage Vx and substrate voltage Vss utilizes a junction breakdown which occurs between the P+ diffused region 3 and n type substrate 4 (or n type well) in case of a static electricity being transferred into the substrate voltage Vss, and a P+/n junction diode formed between the P+ diffused region 2 and n type substrate 4 (or n type well) in case of the static electricity being transferred into the input voltage Vx.
However, the electrostatic discharge protection device as shown in FIG. 1 is disadvantageous in that it does not have electrostatic discharge protection functions between the input voltage Vx and power supply voltage Vcc and between the power supply voltage Vcc and substrate voltage Vss. If the construction as shown in FIG. 1 is formed between the power supply voltage Vcc and input voltage Vx and between the power supply voltage Vcc and substrate voltage Vss to proxide electrostatic discharge protection function for the power supply voltage Vcc, while such functions can be achieved, this results in increasing the size of the chip. Further, since semiconductor integrated circuits having a multi-power supply electrode such as a synchronous DRAM, a word augmented DRAM, a video RAM or a liquid crystal display, have various power supply pads, it is impossible to completely protect such a semiconductor integrated circuit using only the device shown in FIG. 1 from static electricity transferred into the chip externally. In addition, it is difficult to realize the complete protection function without increasing the size of the chip.
Referring to FIG. 1(B), when static electricity is transferred into the substrate voltage Vss, a backward biased junction is formed between the P+ type diffused region 2 and n type bulk 4, and high temperature is thereby concentrically generated in region 10 as indicated by a dashed line. If the temperature of a silicon single crystal exceeds 620.degree. C., the polysilicon in the gate electrode 1, melts into the bulk and thus becomes fused with the bulk, which causes the gate electrode 1 and bulk 4 to be short-circuited.